Exemplary load driving circuits are disclosed in JP 2014-175994 A (patent document 1). According to patent document 1, for switching over connection of a pull-down resistor in a configuration, which is not provided with a separate power supply source, a pull-down resistance element is validated to function as a pull-down resistor in a normal operation and is invalidated to control a gate terminal into a high impedance state at leak test time. The load driving circuit thus controls switchover of the resistor element without using a high-voltage power supply source and a negative power source.
The load driving circuit according to patent document 1 is capable of driving stably a load when a normal power supply voltage is supplied stably. However, when a main power supply voltage is activated, the main power supply voltage is unstable at the time of activation and the load driving circuit is likely to operate erroneously.
For example, in a case that the load driving circuit is configured with a MOS transistor as an output transistor, the MOS transistor is likely to turn on by itself in response to a rapid application of the main power supply voltage thereby causing malfunction of the load driving circuit. To counter this problem, it is proposed to pull down or pull up the gate of the MOS transistor by a resistor. If the gate is pulled down continuously, an output signal waveform of the MOS transistor is likely to be distorted or a quality inspection on the gate of the MOS transistor is likely to be impeded. To solve this problem, it is proposed to invalidate the pull-down by continuously supplying a current to a resistor. This current supply consumes more current.
It is alternatively proposed to prevent the malfunction by initializing the load driving circuit by using a separate logic circuit at the activation time of power supply. When the logic circuit operates with a sub-power supply voltage (for example, logic power supply voltage) of a sub-power supply circuit, which uses the main power supply voltage, it is hard to assure the circuit operation until the sub-power supply voltage rises to a voltage, which assures a normal operation. When the sub-power supply voltage rises with a large delay from a rise of the main power supply voltage, the sub-power supply circuit operates erroneously until it starts to operate normally.
It is further proposed in JP H08-162931 A (patent document 2) to prevent the malfunction described above by a differential circuit of a series circuit of a resistor and a capacitor. However, the capacitor need to have a large capacitance and not suitable for incorporation into a semiconductor integrated circuit.